1. Field of the Invention
The present invention relates to a dc balance-value calculation circuit, used in a recording signal generator for performing the block coding of original data to generate a code word and generating a recording signal based on the code word, provided for calculating a dc balance value representing a shift in the dc balance of the recording signal.
2. Description of the Related Art
When digital data "1" or "0" in the form of the presence or absence of a bit is recorded on a recording medium such as an optical disc, an interval with "0", namely, an interval during which no bit is recorded may be generated for a long period, which is disadvantageous to reproduction of a clock and so forth. Accordingly, conventional modulation called "block coding" is used in which original data is separated into a plurality of data composed of x bits (where x is an integer equal to 2 or greater), and each data of x bits is converted into data composed of y bits (where y.gtoreq.x). For example, digital video discs (DVDs) employ eight-to-sixteen modulation in which original data is separated into a plurality of data composed of eight bits, and each eight-bit data is correlated with the corresponding sixteen-bit data. In the block coding, x-bit data to be coded is called a "data symbol", while y-bit coded data is called a "code word".
FIG. 5 shows a block diagram of a DVD master disc production system. This DVD master disc production system includes a storage unit 101 for reproducing and holding original data, a data converter 102 as a recording signal generator for converting the data reproduced by the storage unit 101 into a recording signal to be recorded on a master disc, and a cutting unit 103 for cutting the master disc in accordance with an output signal from the data converter 102. The storage unit 101 reproduces the original data from an original data-recorded storage medium produced in a studio or the like, such as a tape. A tape streamer, a hard disc drive or the like is used as the storage unit 101. The data converter 102 performs processes such as adding an error correction code to the data reproduced by the storage unit 101, and converts the data into the recording signal to be recorded on the master disc by using the eight-to-sixteen modulation.
FIG. 6 shows a block diagram of the data converter 102 shown in FIG. 5. The data converter 102 includes a communication interface unit 111 for inputting the data from the storage unit 101 to the data converter 102, a data processor 112 for performing processes such as adding the error correction code to the data input by the communication interface unit 111, a modulator 113 including an eight-to-sixteen modulation circuit for performing the eight-to-sixteen modulation of output data from the data processor 112, an output circuit 114 for generating a recording signal based on output data from the modulator 113 and outputting the recording signal, and a central processing unit (CPU) 115 for controlling the communication interface unit 111, the data processor 112 and the modulator 113.
In the data converter 102, the data from the storage unit 101 is input by the communication interface unit 111 to the data processor 112 which performs processes such as adding the error correction code to the input data, and the eight-to-sixteen modulation of the data from the data processor 112 is performed by the modulator 113. The output circuit 114 generates the recording signal, based on the data modulated by the modulator 113, and outputs it to the cutting unit 103 shown in FIG. 5. The CPU 115 controls the communication interface unit 111, the data processor 112 and the modulator 113 so that the recording signal to be recorded on the master disc by the cutting unit 103 is continuously output by the output circuit 114.
FIG. 7 shows a block diagram of the eight-to-sixteen modulation circuit in the modulator 113 shown in FIG. 6. Although the eight-to-sixteen modulation circuit is actually complicated, it is simplified in FIG. 7 unless the simplification affects the description of the present invention. The eight-to-sixteen modulation circuit includes two eight-to-sixteen conversion tables 121 and 122 for respectively converting an input 8-bit data symbol into a 16-bit code word, a digital-sum-value/digital-sum-variation (DSV) calculation circuit 123 for calculating a dc balance value (hereinafter referred to as a "DSV") representing a shift in the dc balance of the recording signal, based on a code word output from the eight-to-sixteen conversion table 121, a DSV calculation circuit 124 for calculating a DSV, based on a code word output from the eight-to-sixteen conversion table 122, a switch 125 for selecting either of the code words output from the eight-to-sixteen conversion tables 121 and 122 before outputting the selected code word, a comparator circuit 126 for controlling the switch 125 so that either code word having a smaller absolute value is selected by comparing the calculations obtained by the DSV calculation circuits 123 and 124, and a parallel-to-serial (P/S) conversion circuit 127 for performing the P/S conversion of the code word output from the switch 125 before outputting it. The eight-to-sixteen conversion table 121 or 122 is realized by, e.g., a read only memory (ROM).
FIG. 8 shows an example of the contents of the eight-to-sixteen conversion table 121 or 122. The eight-to-sixteen modulation must have the condition that, between consecutive inverted bits "1" and "1", there are inserted at least two non-inverted bits "0", in other words, there is a series of at least two non-inverted bits "0". The contents of the eight-to-sixteen conversion table 121 or 122 are prepared accordingly.
Here the DSV will be described. By letting the condition of the recording signal waveform when it is at high level and the condition of it when it is at low level represent +1 and -1, respectively, the DSV is the total of these values. Accordingly, the DSV represents a shift in the dc balance of the recording signal, which influences a servocircuit in a unit for reproducing a signal from a disc. Thus, preferably, the absolute value of the DSV is as small as possible.
FIG. 9 shows a relationship established by the code word in the eight-to-sixteen modulation, the output waveform (recording signal) from the output circuit 114 corresponding to the code word, and DSVs. FIG. 9(a) shows time separations in units of one bit and a code-word unit of sixteen bits. FIG. 9(b) shows an example of the code word. FIG. 9(c) shows the output waveform corresponding to the code word shown in FIG. 9(b). The output waveform is inverted when "1" appears in the code word. This example assumes that the end of the pattern of the last code word was at low level. FIG. 9(d) shows the DSVs corresponding to the code word shown in FIG. 9(b). This case assumes that the DSV at the end of the pattern of the last code word was "0".
The two eight-to-sixteen conversion tables 121 and 122 shown in FIG. 7 are used to select the code word so that the absolute value of the DSV is minimum. Therefore, in the two eight-to-sixteen conversion tables 121 and 122, mutually different code words are defined for at least some of the data symbols.
In the eight-to-sixteen modulation circuit shown in FIG. 7, the eight-to-sixteen conversion tables 121 and 122 convert input 8-bit data symbols into 16-bit code words, and the code words are input to the switch 125. The DSV calculation circuits 123 and 124 calculate DSVs, based on the code words output from the eight-to-sixteen conversion tables 121 and 122. The comparator circuit 126 compares the calculations obtained by the DSV calculation circuits 123 and 124. The switch 125 is controlled so that the DSV having a smaller absolute value is selected. When the absolute values of the DSVs obtained by the DSV calculation circuits 123 and 124 are equal, the comparator circuit 126 controls the switch 125 to select either predetermined output or either output having been selected from the outputs of the eight-to-sixteen conversion tables 121 and 122. The code word output from the switch 125 is converted from the parallel to the serial form by the P/S conversion circuit 126, and is output as serial data. In the above manner the eight-to-sixteen modulation circuit shown in FIG. 7 performs the eight-to-sixteen conversion so that the absolute value of the DSV is least.
Next, referring to a method for calculating a DSV, calculation of a DSV based on a new code word requires the former DSV and information on whether the former output waveform was at high level or low level. The information on whether the former output waveform was at high level or low level is needed to determine whether the new word heading when it is "0" is changed to +1 or -1. Here, by letting the DSV change determined by only the n-th code word be .DELTA.DSV'(n), and Sign representing whether the former waveform is at high level or low level be Sign(n-1), the DSV(n) which is the DSV at the termination of the n-th code word is expressed by the following equation: EQU DSV(n)=DSV(n-1)+(Sign(n-1)).multidot.(.DELTA.DSV'(n))
Concerning the maximum DSV, the maximum DSV is controlled by the algorithm of the eight-to-sixteen modulation so as to be equal to .+-.1024 or less. Thus, in order to realize the DSV calculation circuit by hardware, twelve bits are needed including sign bits. An example of the DSV calculation circuit enabling DSV calculation by hardware is shown in FIG. 10.
The DSV calculation circuit shown in FIG. 10 includes a reference table 131 to which the input n-th Code Word(n), and Sign(n-1) determined by the (n-1l)-th code word are input and which outputs a DSV change .DELTA.DSV(n) caused by the n-th code word obtained in consideration of Sign(n-1) determined by the (n-1)-th code word, and Sign(n) determined by the n-th code word, where .DELTA.DSV(n) is a value corresponding to (Sign(n-1)) in the above equation. The DSV calculation circuit shown in FIG. 10 also includes: a 12-bit adder 132 for calculating DSV(n) as the DSV at the termination of the n-th code word by adding DSV(n-1) as the DSV at the termination of the (n-1)-th code word and .DELTA.DSV(n); a latch 133 for holding and outputting the output DSV(n) of the 12-bit adder 132, and supplying it to the 12-bit adder 132 when the subsequent DSV is calculated; and a latch 134 for holding Sign(n) output from the reference table 131, and supplying it to the reference table 131 when the subsequent DSV is calculated.
In the DSV calculation circuit shown in FIG. 10, the input n-th Code Word(n), and the former Sign(n-1) output from the latch 134 are input to the reference table 131, and they are converted by the reference table 134 into the DSV change .DELTA.DSV(n) (with a 12-bit code) caused by the n-th code word and Sign(n) for the next. .DELTA.DSV(n) is added to DSV(n-1) as the last DSV by the 12-bit adder 132, and the result is held by the latch 133. The output of the latch 133 is a DSV to be sought. In addition, Sign(n) is also held by the latch 134 for the next, and is supplied to the reference table 131.
According to the DSV calculation circuit shown in FIG. 10, the reference table 131 is large as it has inputs of seventeen bits and outputs of thirteen bits, and the adder 132 has twelve bits. Thus, the size of the whole DSV calculation circuit is disadvantageously large.
Next, a DSV calculation circuit for calculating the DSV for each bit of a code word by using a counter without using an adder will be mentioned. An example of the DSV calculation circuit is shown in FIG. 11. The DSV calculation circuit includes a selector 141 for sequentially outputting the input n-th Code Word(n) bit by bit from its head in the form of code bits(m) in accordance with a clock clk (where m represents the bit order from the head). The condition of each bit in the code bits(m) when it is "1" means the inversion of an output waveform, and the condition of it when it is "0" means the non-inversion of the output waveform. The DSV calculation circuit shown in FIG. 11 includes: a logical circuit 142 for carrying out a logical operation with the code bits(m) output from the selector 141, the last code bits(m-1), and Sign(n:m) representing whether the last code bits(m) are at high level or low level, whereby outputting a count-up signal "Up", a countdown signal "Down" and Sign(n:m) of the code bits(m); a latch 143 operating in accordance with the clock clk for holding Sign(n:m) output from the logical circuit 142, and supplying it to the logical circuit 142 when the subsequent code bits(m+1) are input; and a 12-bit counter 144 operating in accordance with the clock clk for counting up when the count-up signal Up is "1" and counting down when the countdown signal Down is "1", whereby outputting DSV(n:m) as the DSV of the code bits(m) for the n-th code word.
In the DSV calculation circuit shown in FIG. 11, the input n-th Code Word(n) is sequentially output bit by bit from its head in the form of the code bits(m) in accordance with the clock clk by the selector 141, and the output is input to the logical circuit 142. The logical circuit 142 outputs the count-up signal Up, the count-down signal Down and Sign(n:m) by carrying out a logical operation with the code bits(m) output from the selector 141 and Sign(n:m-1). The Sign(n:m) output from the logical circuit 142 is held by the latch 143, and is supplied to the logical circuit 142 when the subsequent code bits(m+1) are input. The count-up signal Up and the count-down signal Down are input to the 12-bit counter 144. The 12-bit counter 144 operating in accordance with the clock clk outputs DSV(n:m) as the DSV for the code bits(m) from the n-th code word by counting up when the count-up signal Up is "1", and counting down when the count-down signal Down is "1". Although the DSV calculation circuit shown in FIG. 11 is smaller in size than the DSV calculation circuit shown in FIG. 10, it needs a long period of sixteen clocks for DSV calculation for one code word. Accordingly, an eight-to-sixteen modulation circuit as shown in FIG. 7 disadvantageously reduces the time for processing based on a DSV calculation by the comparator 126.